View IDT74FCT162H272CT_297014.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IDT74FCT162H272AT/CT FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
FEATURES:
* * * * * * * * * *
IDT74FCT162H272AT/CT
DESCRIPTION:
0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1A (max.) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Balanced Output Drivers: 24mA Reduced system switching noise Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25C Bus Hold retains last active bus state during 3-state Eliminates the need for external pull up resistors Available in SSOP and TSSOP packages
The FCT162H272T synchronous tri-port bus exchangers are high-speed, bidirectional,12-bit, registered, bus multiplexers for use in synchronous memory interleaving applications. All registers have a common clock and use a clock enable (CExxx) on each data register to control data sequencing. The output enables and mux select (OEA, OEB and SEL) are also under synchronous control allowing direction changes to be edge triggered events. The tri-port bus exchanger has three 12-bit ports. Data may be transferred between the A port and either/both of the B ports. The clock enable (CE1B, CE2B, CEA1B and CEA2B) inputs control the data storage. Both B ports have a common output enable (OEB) to aid in synchronously loading the B registers from the B port. The FCT162H272T has balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors. The FCT162H272T has "Bus Hold" which retains the input's last state whenever the input goes to high impedance. This prevents "floating" inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
CEA1B CLK
CE A-1B REGISTER Q D
12
1B1:12
CE1B 12 SEL OEB OEA A1:12 12 CE2B 12 12 CEA2B M1 U X0 C ONTROL REGISTER 12
CE 1B-A REGISTER D Q
12
CE
2B-A REGISTER D 12
Q
CE A-2B REGISTER Q D
12
2B1:12
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
(c) 2002 Integrated Device Technology, Inc.
NOVEMBER 2002
DSC-3071/1
IDT74FCT162H272AT/CT FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
CEA1B CEA2B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 OEA SEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SO56-1 SO56-2 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CE1B CE2B 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 OEB CLK
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) TSTG IOUT Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to 7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA VTERM(3) Terminal Voltage with Respect to GND
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT.
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. 6 8 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
SSOP/ TSSOP TOP VIEW
2
IDT74FCT162H272AT/CT FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Signal A(1:12) 1B(1:12) 2B(1:12) CLK CEA1B CEA2B CE1B CE2B SEL OEA OEB I/O I/O I/O I/O I I I I I I I I Description Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.(1) Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.(1) Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.(1) Clock Input Clock Enable Input for the A-1B Register. If CEA1B is LOW during the rising edge of CLK, data will be clocked into register A-1B (Active LOW). Clock Enable Input for the A-2B Register. If CEA2B is LOW during the rising edge of CLK, data will be clocked into register A-2B (Active LOW). Clock Enable Input for the 1B-A Register. If CE1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A (Active LOW). Clock Enable Input for the 2B-A Register. If CE2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A (Active LOW). 1B or 2B Path Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port. Synchronous Output Enable for A Port (Active LOW). Synchronous Output Enable for 1B Port and 2B Port (Active LOW).
NOTE: 1. On FCT162H272T these pins have "Bus Hold". All other pins are standard inputs, outputs or I/Os.
FUNCTION TABLES(2)
Inputs 1B H L X X X X X 2B X X X H L X X SEL H H H L L L X CE1B L L H X X X X Inputs A H L H L H L X X X CEA1B L L L L H H H X X CEA2B L L H H L L H X X OEB L L L L L L L H L CLK 1B H L H L B(1) B(1) B(1) Z Active CE2B X X X L L H X OEA L L L L L L H CLK Output A H L A(1) H L A(1) Z Outputs 2B H L B(1) B(1) H L B(1) Z Active
NOTES: 1. Output level before the indicated steady-state input conditions were established. 2. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance = LOW-to-HIGH Transition
3
IDT74FCT162H272AT/CT FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (BUS HOLD)
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 10%
Symbol VIH VIL IIH Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) IIL Input LOW Current(4) IBHH IBHL IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Bus-hold Sustain Current(4) High Impedance Output Current (3-State Output pins)(5, 6) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Max. VIN = GND or VCC VCC = Max., VO = VCC = Max. Standard Input(5) Standard I/O(5) Bus-hold Input Bus-hold I/O Standard Input(5) Standard I/O(5) Bus-hold Input Bus-hold I/O Bus-hold Input VCC = Min. VI = 2V VI = 0.8V VO = 2.7V VO = 0.5V VCC = Min., IIN = -18mA GND(3) -- VI = GND Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC Min. 2 -- -- -- -- -- -- -- -- -- -50 50 -- -- -- -80 -- -- Typ.(2) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -0.7 -140 100 5 Max. -- 0.8 1 1 100 100 1 1 100 100 -- -- 1 1 -1.2 -250 -- 500 V mA mV A A A Unit V V A
OUTPUT DRIVE CHARACTERISTICS
Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) VCC = 5V, VIN = VIH or VIL, VO VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. This test limit for this parameter is 5A at TA = -55C. 6. Does not include Bus-Hold I/O pins.
Min. 60 -60
Typ.(2) 115 -115 3.3 0.3
Max. 200 -200 -- 0.55
Unit mA mA V V
= 1.5V(3) IOH = -24mA IOH = 24mA
2.4 --
4
IDT74FCT162H272AT/CT FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open One Output Port Enabled CExx = GND One Input Bit Toggling One Output Bit Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OEx = CExx = GND One Input Bit Toggling One Output Bit Toggling fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OEx = CExx = GND Twelve Input Bits Toggling Twelve Output Bits Toggling fi = 2.5MHz 50% Duty Cycle Min. -- -- Typ.(2) 0.5 60 Max. 1.5 100 Unit mA A/ MHz
VIN = VCC VIN = GND
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
0.6
1
mA
VIN = 3.4V VIN = GND
--
1.1
2.5
VIN = VCC VIN = GND
--
2.1
3.5(5)
VIN = 3.4V VIN = GND
--
5.4
13.3(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
5
IDT74FCT162H272AT/CT FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT162H272AT Symbol tPLH tPHL tPLH tPHL Propagation Delay CLK to 1Bx or CLK to 2Bx Propagation Delay CLK to Ax SEL Stable CExB Enabled SEL Changing CExB Disabled SEL Changing CExB Enabled tPZH tPZL tPHZ tPLZ tSU tSU tSU tSU tH tH tH tW tSK(o) Output Enable Time CLK to Ax, CLK to 1Bx, or CLK to 2Bx Output Disable Time CLK to Ax, CLK to 1Bx, or CLK to 2Bx Set-Up Time, HIGH or LOW Data to CLK Set-Up Time, OEA to CLK, OEB to CLK Set-Up Time, SEL to CLK Set-Up Time, CEA1B to CLK, CE1B to CLK, CE2B to CLK, or CEA2B to CLK Hold Time, CLK to Data Hold Time, CLK to OEA, CLK to OEB, CLK to SEL Hold Time, CLK to CEA1B, CLK to CE1B, CLK to CE2B, CLK to CEA2B Pulse Width, CLK HIGH(3) Output Skew(4) 3 -- -- 0.5 3 -- -- 0.5 ns ns 0 -- 0 -- ns 0 0.5 -- -- 0 0.5 -- -- ns ns 2 2 2 2 -- -- -- -- 2 2 2 2 -- -- -- -- ns ns ns ns 1.5 6.4 1.5 6 ns 1.5 7.7 1.5 6.8 ns 1.5 7.6 1.5 6.6 ns 1.5 6 1.5 5.4 ns Parameter Condition(1) CL = 50pF RL = 500 1.5 6 1.5 5.4 ns Min.(2) 1.5 Max. 5.8 FCT162H272CT Min.(2) 1.5 Max. 5.2 Unit ns
NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
6
IDT74FCT162H272AT/CT FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 7.0V 500 V IN Pulse Generator D.U.T. 50pF RT 500 CL V OUT
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
DATA INPUT tSU TIM ING INPUT ASYNCHRONOUS CONTROL PRES ET CLEA R ETC. SYNCHRONOUS CONTROL PRES ET CLEA R CLOCK ENABLE ETC. tREM
tH
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE
1.5V
1.5V
tSU
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE SAM E PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE P HASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V DISABLE 3V CONTROL INPUT tPZL OUTPUT NORM ALLY LOW SW ITCH CLOSED tPZH OUTPUT NORM ALLY HIGH SW ITCH OPEN 3.5V 1.5V 0.3V tPHZ 0.3V 1.5V 0V 0V VOH tPLZ 1.5V 0V 3.5V VOL
Propagation Delay Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
7
IDT74FCT162H272AT/CT FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
ID T FC T XX Temp. R ange XXX Family XXXX X Bus-Hold Device Type XX Package
PV PA
Shrink Sm all Outline Package (SO56-1) Thin Shrink Sm all Outline Package (SO56-2)
272AT 12-Bit Synchronous Bus Exchanger 272C T
H
Bus-hold
162
Double-Density, 5 Volt, Balanced Drive
74
-40C to +85C
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
8

▲Up To Search▲

Price & Availability of IDT74FCT162H272CT

	To Download IDT74FCT162H272CT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .